Method of making a multi-bit nanocrystal memory

ABSTRACT

A manufacturing method for an improved memory cell having a pair of non-volatile memory transistors with each transistor using a nanocrystal gate structure, the transistor pair constructed between a pair of bit line polysilicon depositions. Between the pair of non-volatile memory transistors, a word line device is interposed, allowing serial linkage of the pair of non-volatile memory transistors.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of pending U.S. patent application Ser.No. 11/001,936 filed Dec. 2, 2004.

TECHNICAL FIELD

The invention relates to non-volatile memory transistor construction,and, more specifically, to a manufacturing method for a transistoremploying nanocrystals.

BACKGROUND ART

Non-volatile memory designs continue to improve with technologicaladvancements. Floating gate and MONOS (metal/polysilicon oxide nitrideoxide silicon) are types of non-volatile memories. In conventionalfloating gate structures, charge is stored on to a floating gate, byeither Fowler-Nordheim tunneling or by source side injection. The celloperation is governed by electron charge storage on an electricallyisolated floating gate. The amount of charge stored modulates the memorycell's transistor characteristic. Because the only electrical connectionto the floating gate is through capacitors, the memory cell can bethought of as a linear capacitor network with an attached N-channeltransistor. Any charge present on the floating gate is retained due tothe inherent Si-SiO₂ energy barrier height, leading to the non-volatilenature of the memory cell.

MONOS memory cells, in comparison to standard floating gate cells, mayhave faster program times and higher densities. In MONOS memory cellsusing sidewall spacer structures, a source side electron injectionapproach is faster and may require lower voltages than electrontunneling methods used for a standard floating gate design. U.S. Pat.No. 6,686,632, to Ogura et al. describes a dual bit MONOS memory havinga twin cell structure. The cell structure is realized by placingsidewall control gates over a composite of oxide nitride oxide (ONO).Both sides of a word gate and control gates are formed using adisposable sidewall process. During construction of this device, asidewall spacer is required for the word gate to accommodate the ONO andsource side injection structure.

Newer processes that may be used in non-volatile memory designs alsocontinue to be developed. For example, metal nanocrystal memories havebeen utilized to enhance the performance of memory cell devices toimprove the work function. In a nanocrystal non-volatile storage device,charge is not stored on a continuous floating gate layer. Instead, alarge number of discrete mutually isolated nanocrystals are contained ona semiconductor layer. Nanocrystals may be employed in storing smallamounts of electrical charge, even being able to store a single, or asmall number, of atoms. In theory, smaller transistors may be madebecause structures containing nanocrystal charge storage “dots” might bemade exceedingly small.

A downside to using nanocrystals has been high power consumption due torefresh requirements, short retention time, and high capacitance. U.S.Pat. No. 6,165,842, to Shin et al. describes a method for fabricating anonvolatile memory device using crystal dots. A tunneling dielectric, athin amorphous silicon film, a polysilicon layer having nanocrystals, adielectric layer, and a polysilicon film are formed. The method developsa nonvolatile memory cell gate structure having dimensions limited bythe resolution of optics or photoresist materials used inphotolithography and must develop a multitude of layers to support andconstruct a nanocrystal layer.

Such devices are therefore difficult to manufacture because nanocrystalsare many times smaller than photolithography resolution limits currentlyused in manufacturing integrated circuits.

SUMMARY OF THE INVENTION

The present invention is a manufacturing method for an improved memorycell device employing nanocrystals to reduce an overall size of eachmemory cell gate, and therefore reduce the overall integrated circuit ordie size of a memory circuit. In accordance with the present invention,a nanocrystal layer is used in the construction of a dual bitnon-volatile memory structure. A plurality of trenches are developed toreduce the gate area or each memory cell which uses a nanocrystal chargestorage region. Charge is transferred through a thin tunneling barrierto the nanocrystals. The method forms a memory cell gate using aplurality of offset trenches to expose and remove a portion of ananocrystal layer to develop a nanocrystal gate area having at least onedimension that is smaller than current photolithography resolutionlimits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross section of an exemplary beginning structure of asubstrate with a nanocrystal stack, and a first polysilicon layer formedabove it. Also shown are a formed oxide layer, nitride layer, oxidelayer and a patterned photoresist mask.

FIG. 1B is an enlarged cross section al area of the nanocrystal stack ofFIG. 1A, comprised of a tunnel oxide layer, a nanocrystal layer, and acontrol oxide layer.

FIG. 2 is a cross section of FIG. 1A after a portion of the oxidenitride oxide have been removed and the patterned photoresist mask hasbeen removed.

FIG. 3 is a cross section of FIG. 2 after a fifth oxide has been formedon the sidewalls of oxide mesa structures.

FIG. 4 is a cross section of FIG. 3 after an exposed portion of thefirst polysilicon layer has been selectively removed.

FIG. 5 is a cross section of FIG. 4 after a first dopant has been formedin the underlying substrate.

FIG. 6 is a cross section of FIG. 5 after a portion of the nanocrystalstack has been selectively removed and a second dopant has beenselectively formed in the exposed substrate.

FIG. 7 is a cross section of FIG. 6 after a sixth oxide has been formedover the dopant area and mesa structures.

FIG. 8 is a cross section of FIG. 7 after a portion of the sixth oxidehas been selectively removed and a third dopant has been selectivelyformed in the exposed substrate.

FIG. 9 is a cross section of FIG. 8 after a second polysilicon layer hasbeen formed.

FIG. 10 is a cross section of FIG. 9 after a portion of the secondpolysilicon layer has been selectively removed.

FIG. 11 is a cross section of FIG. 10 after a fifth oxide layer has beenformed.

FIG. 12 is a cross section of FIG. 11 after a portion of the seventhoxide layer has been selectively removed.

FIG. 13 is a cross section of FIG. 12 after the nitride structure hasbeen removed.

FIG. 14 is a cross section of FIG. 13 after a portion of the remainingoxide layers and a portion of the second polysilicon layer have beenselectively removed.

FIG. 15 is a cross section of FIG. 14 after an eighth oxide layer hasbeen deposited.

FIG. 16 is a cross section of FIG. 15 after a portion of the eighthoxide layer and the nanocrystal stack has been removed.

FIG. 17 is a cross section of FIG. 16 after a word line gate oxide hasbeen formed above the exposed substrate.

FIG. 18 is a cross section of FIG. 17 after a third polysilicon layerhas been deposited.

FIG. 19 is a cross section of FIG. 18 after a portion of the thirdpolysilicon layer and top oxide have been removed.

FIG. 20 is a cross section of the memory cell structures indicatingvarious memory cell structure elements.

FIG. 21 is a circuit diagram of a dual memory cell as shown in FIG. 20.

DETAILED DESCRIPTION OF THE INVENTION

Collectively, individual nanocrystals in a nanocrystal memory gate cancontrol the channel conductivity of a memory cell. Each nanocrystalindividually stores a small number of electrons. One of the advantagesof a nanocrystal charge storage gate is an ability to use thinner tunneloxides and shorter channel lengths and therefore, a smaller cell areamay be developed. In addition, the stored charge (electrons) in ananocrystal charge storage gate may be directed to a specific areawithin the storage gate area and can be configured to store a singlelogic state (bit) or multiple logic states (bits) within a given cell.

With reference to an exemplary process beginning with FIG. 1A, asubstrate 10 having a p-well or p-type substrate material is used. Thep-well is developed by doping a surface of the substrate with, forexample, boron. A nanocrystal stack 20 is formed above the substrate 10.The nanocrystal stack 20, FIG. 1B, is composed of a thin tunnel oxidelayer 21 (a first oxide), a thin nanocrystal layer 22, and a thincontrol oxide layer 23 (a second oxide). In a specific embodiment, thenanocrystal stack 20 will have an average thickness of approximately120-180 Angstroms. The tunnel oxide layer 21 may generally have athickness of 20-50 Angstroms; the nanocrystal layer 22 may generallyhave a thickness of 20-60 Angstroms; and the control oxide layer 23 maygenerally have a thickness of 60-100 Angstroms.

The nanocrystals may be comprised of any material such as a silicon,germanium, Si-Ge, or metal, and the nanocrystal layer will typicallyhave an approximate 50% to 75% area coverage of nanocrystals. In aspecific embodiment, the nanocrystal area coverage will be approximately60%. The nanocrystal layer 22 may be fabricated by various techniquesincluding chemical vapor deposition, low energy implantation, or byaerosol formation.

With reference again to FIG. 1A, in the formation of a memory cellstructure, a first polysilicon layer 30 is formed over the nanocrystalstack 20 (tunnel oxide 21, nanocrystal 22, and control oxide 23 layers).

Above the first polysilicon layer 30 a third oxide layer 40, a nitridelayer 41, and a fourth oxide layer 42 are formed. Referring to FIG. 2, aportion of the fourth oxide layer 42, nitride layer 41, and third oxidelayer 40 are then selectively removed for example, using a patternedphotoresist mask 50 and an etch process. After the patterned photoresistmask 50 is removed, a sacrificial mesa (or island) structure 51 remains,composed of portions of the third oxide layer 40, nitride layer 41, andthe fourth oxide 42.

In reference to FIG. 3, a fifth oxide layer 43 is formed over theexposed edges or sidewalls of the sacrificial mesa structure 51, forexample using a chemical vapor deposition of oxide followed by, forexample patterning and an anisotropic etch process, leaving a fifthoxide layer 43 on both sides of the sacrificial mesa structure 51 andover the top portion of the mesa structure, depending upon thedeposition process used. The fifth oxide layer 43 will be used as a hardmask during a subsequent removal or etch process. Next, a portion of theunderlying first polysilicon layer 30 is removed, for example by aselective etch process. The removal or etch process selectively removesa portion of the first polysilicon layer 30 and forms a first trench 52in the first polysilicon layer 30 as shown in FIG. 4.

Next, several steps will be used to develop channel, source, and drainareas for a dual cell memory structure. With reference to FIG. 5, afirst n-type doped area 54 is formed in the substrate 10, for example byhigh angle tilt ion implantation, approximately near the bottom of thefirst trench 52 or approximately in an area where the nanocrystal stack20 is exposed. The mesa structure 51 and the first trench 52 will beused as a self-aligning mask and may affect the shape and depth of thefirst doped area 54 under the nanocrystal stack 20. The first doped area54 extends partially under the remaining first polysilicon layer 30 andnanocrystal stack 20.

Next, referring to FIG. 6, the exposed portion of the nanocrystal stack20 in the first trench 52 is removed. In an alternative embodiment anunderlying portion of the substrate 10 may be over-etched to form adepression in the first doped area 54. A second doped area 55 is formedin the area proximate to the first doped area 54. Referring to FIG. 7, asixth oxide layer 44 is formed over the previously described structuresand subsequently etched to expose the second doped area 55 approximatelyat the bottom of the first trench 52. A third doped area 56 is thenformed in the substrate 10 near the bottom of the first trench 52 asshown in FIG. 8.

Referring to FIG. 9, a second polysilicon layer 31 is then formed overthe doped areas 54, 55, 56 of the substrate 10 and mesa structures 51,filling the first trench 52. Next, an upper portion of the secondpolysilicon layer 31 is then selectively removed, leaving a portion ofthe first trench 52 filled with a portion of the second polysiliconlayer 31 as shown in FIG. 10. Next, referring to FIG. 11, a seventhoxide layer 45 is formed, such as a TEOS oxide layer, covering the abovedescribed structures and features. A portion of the seventh oxide layer45 is subsequently removed. A CMP (chemical mechanical planarization)step may be performed to remove a portion of the seventh oxide 45. Anexemplary CMP step may also be performed to remove a portion of theseventh oxide layer 45. A portion of the nitride layer 41 under theseventh oxide layer has been exposed as shown in FIG. 12.

Next, with reference to FIG. 13, the remaining portion of the nitridelayer 41 feature is removed, for example by using a high selectivity wetetch technique. Removal of the remaining nitride layer 41 providesbreaks 46 in the remaining oxide layer 47. Referring to FIG. 14, aportion of the remaining oxide layer 47 is removed, and a portion of thefirst polysilicon layer 30 is also removed, forming second trenches 57in the first polysilicon layer 30. In one embodiment, the second trenchis offset from the first trench location by a distance that is smallerthan a photolithography resolution limit in an optical process. Theunderlying control oxide 23 (see FIG. 1B) in the nanocrystal stack 20may be used as an etch stop for the polysilicon etch.

Referring to FIG. 15, an eighth oxide 48 is formed over the sidewalls ofthe remaining first polysilicon layer, and the control oxide layer 23 ofthe nanocrystal stack 20. In one embodiment, the eighth oxide 48 may beformed by a chemical vapor deposition process. Next, with reference toFIG. 16, the eighth oxide 48 at the bottom of the second trench isselectively removed. The removal process also removes a portion of thethin control oxide layer 23 in the nanocrystal stack 20, for exampleusing an etch process, to expose the nanocrystal layer 22. The exposedportion of the nanocrystal layer 22 is removed to expose the underlyingtunnel oxide 21 and, the exposed tunnel oxide 21 is also removed.

With reference to FIG. 17, a gate structure 24 for a nonvolatile memorycell has now been formed. Using a nanocrystal gate structure provides anadvantage or using thinner tunnel oxides without sacrificing breakdownand leakage parameters, allowing lower operating voltages and/orincreasing operating speed. When hot carriers are injected into thenanocrystal layer 22 (FIG. 1B), there is less carrier scattering, in thedepleted layer underneath the gate and less energy is required to movecarriers into the nanocrystals in the nanocrystal layer 22. Usingnanocrystals within the gate structure 24 also allows the use of shorterchannel lengths and therefore smaller cell sizes. In the formationprocess, removing portions of the nanocrystal stack 20 using atwo-trench approach allows a nanocrystal gate structure to be builthaving dimensions that are smaller compared to developing a gatedirectly from a photoresist mask using, a standard photolithographyprocess. Applying a two-trench formation method provides a process tobuild smaller structures and to reap the technological advantages andimprovements that nanocrystal containing structures have to offer.

Next, a cleaning operation may be performed to prepare the wafer surfacefor a subsequent oxidation step. With continued reference to FIG. 17, agate oxidation step forms a word line gate structure 25. In FIG. 18,after a word line gate structure 25 has been formed, a third polysiliconlayer 32 is formed, filling the second trenches 57. The thirdpolysilicon layer 32 will provide a conductive path for a conventionalword line control device. Referring to FIG. 19, a portion of the thirdpolysilicon layer 32 and an upper portion of the remaining oxide layer48 is then removed, exposing remaining portions of the first polysiliconlayer 30 and the second polysilicon layer 31. For example, a chemicalmechanical planarization step may be performed, and a cleaning processmay be used to prepare the wafer surface for forming additionalpolysilicon or metal interconnections. The exposed portions of the first30, second 31, and third 32 polysilicon layers provide conductive pathsto the underlying structures. The exposed polysilicon 30, 31, 32 will befurther developed or coupled to interconnections including a word line,bit line, and/or control gate line. A variety of subsequent processesmay be performed to form the conductive interconnections to produce anintegrated circuit memory chip.

A basic non-volatile dual memory cell structure of FIG. 20 (withoutinterconnections), is schematically represented in FIG. 21. Two memorycells 70, 71 are serially coupled by a word line device 72 having gateportions 62 and 67. Each memory cell 70, 71 is also coupled to aconductive control gate line 60, 61 and a bit line 64, 68. The drain andsource of each memory cell 70, 71, having a nanocrystal area 65, 66 tostore electrons, provide the functions for a dual non-volatile memorycell structure.

Presented in this description is an exemplary structure and fabricationmethod for a dual multi-bit memory cell. It is to be understood that theabove description is intended to be illustrative, and not restrictive.Those of skill in the art will recognize that the invention can bepracticed with modification and alteration within the spirit and scopeof the appended claims and many other embodiments will be apparent tothose of skill in the art upon reading and understanding the abovedescription. The procedures for formation, for example, the formation ofshallow trench isolation areas, p-well, and n-well are similar toconventional CMOS processing and, although not shown or described, theseprocesses or structures may be used with the invention described. Otherprocesses such as the formation of oxides, polysilicon layers, ornitride layers may be performed by other processes not described butknown to one of skill in the art. Masking processes with exposures,development, and vertical or horizontal etching of layers may beperformed by a variety of processes including chemical etching or ionmilling. The description is thus to be regarded as illustrative ratherthan limiting. The scope of the invention should, therefore, bedetermined with reference to the appended claims, along with the fullscope of equivalents to which said claims are entitled.

1. A method of fabricating a nonvolatile memory cell device, the methodcomprising: forming a nanocrystal layer over a substrate; forming afirst polysilicon layer over said nanocrystal layer; removing a firstportion of said first polysilicon layer, thereby forming a first trenchin said first polysilicon layer; removing a first portion of saidnanocrystal layer, said first portion of said nanocrystal layersubstantially within an area circumscribed by said first trench;removing a second portion of said first polysilicon layer, said secondportion offset from said first trench location by a distance less than aphotolithography resolution limit in an optical process, thereby forminga second trench in said first polysilicon layer; removing a secondportion of said nanocrystal layer, said second portion of saidnanocrystal layer substantially within an area circumscribed by saidsecond trench, thereby forming a nanocrystal gate area having a widththat is smaller than a photolithography resolution limit in an opticalprocess; and forming a plurality of doped areas in said substrates. 2.The method of fabricating the nonvolatile memory cell device of claim 1wherein said nanocrystal layer has an approximate thickness between 20Angstroms and 60 Angstroms.
 3. The method of fabricating the nonvolatilememory cell device of claim 1 wherein a tunnel oxide layer is formedbefore forming said nanocrystal layer and a control oxide layer isformed after forming said nanocrystal layer.
 4. The method offabricating the nonvolatile memory cell device of claim 3 wherein anaverage summed thickness of said tunnel oxide layer, said nanocrystallayer, and said nanocrystal layer is between approximately 120 Angstromsand 180 Angstroms.
 5. The method of fabricating the nonvolatile memorycell device of claim 1 wherein the step of forming said plurality ofdoped areas in said substrate is performed before removing said firstportion of said nanocrystal layer.
 6. The method of fabricating thenonvolatile memory cell device of claim 1 wherein the step of formingsaid plurality of doped areas in said substrate is performed afterremoving said first portion of said nanocrystal layer.
 7. The method offabricating the nonvolatile memory cell device of claim 1 wherein thestep of forming said plurality of doped areas in said substrate furthercomprises forming at least one doped area before removing said firstportion of said nanocrystal layer, and forming at least one other dopedarea in said substrate after removing said first portion of saidnanocrystal layer.
 8. The method of fabricating the nonvolatile memorycell device of claim 1 wherein a second polysilicon layer is formedfilling said first trench in said first polysilicon layer.
 9. The methodof fabricating the nonvolatile memory cell device of claim 8 wherein athird polysilicon layer is formed filling said second trench in saidfirst polysilicon layer.
 10. A method for fabricating a nonvolatile dualmemory cell device comprising: forming a tunnel oxide layer ananocrystal layer and a control oxide layer sequentially on a face of anunderlying substrate thereby forming a nanocrystal stack layer; forminga first polysilicon layer over said nanocrystal stack layer; forming anoxide-nitride-oxide stack layer over said first polysilicon layer;removing a portion of said oxide-nitride-oxide stack layer therebyforming a patterned oxide-nitride-oxide stack layer and exposing aportion of said first polysilicon layer; removing said exposed portionof said first polysilicon layer, forming a first trench in said firstpolysilicon layer and exposing a first portion of said nanocrystal stacklayer; forming at least one doped area in said underlying substratesubstantially beneath said first trench; removing said first exposedportion of said nanocrystal stack layer; forming a second polysiliconlayer thereby filling said first trench in said first polysilicon layer;removing a portion of said second polysilicon layer thereby exposing asidewall portion of said first trench; forming an additional oxide layerover said second polysilicon layer and over said exposed sidewallportion of said first trench; removing a portion of said additionaloxide layer using said nitride in said patterned oxide-nitride-oxidestack layer as a stop; removing a second portion of said additionaloxide layer and removing a second portion of said first polysiliconlayer, said second portion of said additional oxide layer and saidsecond portion of said first polysilicon layer being offset from saidfirst trench location by a distance less than a photolithographyresolution limit in an optical process, thereby forming a second trenchin said first polysilicon layer and exposing a second portion of saidnanocrystal stack layer; and removing said exposed second portion ofnanocrystal stack layer, said second portion of said nanocrystal layersubstantially within an area circumscribed by said second trench therebyforming a nanocrystal gate area having a width that is smaller than aphotolithography resolution limit in an optical process.
 11. The methodof fabricating the nonvolatile memory cell device of claim 10 whereinsaid nanocrystal layer has an approximate thickness between 20 Angstromsand 60 Angstroms.
 12. The method of fabricating the nonvolatile dualmemory cell device of claim 10 wherein an average summed thickness ofsaid tunnel oxide layer said nanocrystal layer, and said nanocrystallayer is between approximately 120 Angstroms and 180 Angstroms.
 13. Themethod of fabricating the nonvolatile dual memory cell device of claim10 wherein the step of forming said at least one doped area in saidunderlying substrate is performed before removing said first exposedportion of said nanocrystal stack layer.
 14. The method of fabricatingthe nonvolatile dual memory cell device of claim 10 wherein the step offorming said at least one doped area in said underlying substrate isperformed after removing said first exposed portion of said nanocrystalstack layer.
 15. The method of fabricating the nonvolatile dual memorycell device of claim 10 wherein forming said at least one doped area insaid underlying substrate further comprises forming a doped area beforeremoving said first exposed portion of said nanocrystal stack layer andalso forming at least one other doped area after removing said firstexposed portion of said nanocrystal stack layer.
 16. The method offabricating the nonvolatile dual memory cell device of claim 10 whereina third polysilicon layer is formed thereby filling said second trenchin said first polysilicon layer.